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机译:包含环路延迟的电荷泵锁相环中基于LMI的参考杂散降低方法
Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road,Taipei, 106, Taiwan ROC;
Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road,Taipei, 106, Taiwan ROC;
jitter peaking; loop delay; linear matrix inequality (LMI); loop bandwidth; phase-locked loop (PLL); reference spur; z-domain;
机译:零电荷泵失配电流跟踪环路,用于降低PLL的参考杂散
机译:迈向通用电荷泵锁相环,使用间接片上方法的抖动估计技术
机译:两级反馈环路电荷泵,可降低CMOS PLL的杂散
机译:具有-240 dB FOM和-80 dBc参考杂散的参考过采样数字锁相环
机译:电荷泵锁相环的片上特性。
机译:具有延迟耦合的数字锁相环的自组织同步理论与实验
机译:一阶数字Bang-bang锁相环中环路延迟和参考时钟抖动的综合影响