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Effective Subblock-Based and Pixel-Based Fast Direction Detections for H.264 Intra Prediction

机译:用于H.264帧内预测的有效的基于子块和基于像素的快速方向检测

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In H.264/AVC intra-frame coding, the rate-distortion optimization (RDO) is employed to select the optimal coding mode to achieve the minimum rate-distortion cost. Due to a large number of combinations of coding modes, the computational burden becomes extremely high in intra-prediction. In this paper, we propose two fast, efficient but reliable direction detection algorithms by computing subblock and pixel direction differences. Both proposed methods effectively estimate the edge direction inside the block to narrow down the predictive modes to reduce the RDO computation. Experimental results show that the proposed methods can reduce the encoding time by about 60% with negligible loss of coding performance. For hardware realization, a fast mode decision VLSI circuit for intra-prediction with the silicon core size of 0.12 $,times,$0.12${hbox {mm}}{2}$ at 0.18-$mu{hbox {m}}$ CMOS technology is implemented. The fast mode decision VLSI in three-stage pipelined architecture operated at 173 MHz can encode 30 fps real-time videos up to Level 5.
机译:在H.264 / AVC帧内编码中,采用速率失真优化(RDO)来选择最佳编码模式以实现最小的速率失真成本。由于编码模式的大量组合,帧内预测的计算负担变得非常高。在本文中,我们通过计算子块和像素方向差异,提出了两种快速,高效但可靠的方向检测算法。两种提出的方​​法都有效地估计了块内部的边缘方向,以缩小预测模式以减少RDO计算。实验结果表明,该方法可以将编码时间减少约60%,而编码性能的损失可以忽略不计。对于硬件实现,一种用于帧内预测的快速模式决策VLSI电路,其硅核尺寸为0.12 $,times,$ 0.12 $ {hbox {mm}} {2} $,0.18- $ mu {hbox {m}} $ CMOS技术得以实施。在173 MHz下运行的三级流水线架构中的快速模式决策VLSI可以对30 fps实时视频进行编码,最高级别为5。

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