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A Fully Digital Phase Modulator With a Highly Linear Phase Calibration Loop for Wideband Polar Transmitters

机译:具有高度线性相位校准环路的全数字相位调制器,用于宽带极性发射器

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This brief presents a digital phase modulator for wideband polar transmitters. It adopts a digital-to-time converter (DTC) and a highly linear phase calibration loop that improves phase resolution for high data-rate systems. The proposed 10-bit DTC consists of a coarse 5-bit cascaded delay line and a fine 5-bit digitally controlled delay line. This DTC achieves a fine delay resolution with digitally controlled varactors and is capable of introducing incremental delays as small as 2.49 ps. A phase calibration loop based on an advanced successive approximation register (SAR) time-to-digital converter (TDC) is nested inside the phase modulator and sets the DTC output phase accurately across the range of input digital codes. The SAR TDC also compensates for any process, voltage, and temperature variations. By using the proposed SAR TDC-based calibration loop, the phase modulator can achieve a high sampling rate and a fine phase resolution. This was possible because the number of phase comparisons of the SAR TDC has been significantly reduced. The phase modulator achieves 0.61 degrees root-mean-square phase error and a 30 MS/s sampling rate at the carrier frequency of 600 MHz while consuming 9.4 mW. This phase modulator is implemented in a 180-nm CMOS technology and occupies 0.19 mm(2).
机译:本简介介绍了一种用于宽带极性发射机的数字相位调制器。它采用了数模转换器(DTC)和高度线性的相位校准环路,可提高高数据速率系统的相位分辨率。提议的10位DTC由粗5位级联延迟线和5位精细数字延迟线组成。该DTC通过数字控制的变容二极管实现了精细的延迟分辨率,并能够引入低至2.49 ps的增量延迟。基于高级逐次逼近寄存器(SAR)时数字转换器(TDC)的相位校准环路嵌套在相位调制器内部,并在整个输入数字代码范围内准确设置DTC输出相位。 SAR TDC还可以补偿任何过程,电压和温度变化。通过使用建议的基于SAR TDC的校准环路,相位调制器可以实现高采样率和精细的相位分辨率。这是可能的,因为SAR TDC的相位比较次数已大大减少。相位调制器在600 MHz的载波频率上实现0.61度的均方根相位误差和30 MS / s的采样率,同时消耗9.4 mW。该相位调制器采用180 nm CMOS技术实现,占地0.19 mm(2)。

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