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Minimizing Impedance Discontinuities In High-speed Pcb Designs

机译:最小化高速PCB设计中的阻抗不连续性

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摘要

A growing number of high-speed standards and proprietary serial protocols are posing major design layout challenges for PCB designers. These serial standards include PCI Express, Serial RapidIO, Gigabit Ethernet, XAUI/HiGig, SONET, CPRI, OBSAI, and a host of others. Serial buses with differential signaling are quickly replacing parallel buses as the demand for high-speed PCB designs increases. Differential signaling uses two output drivers to drive two independent transmission lines. One carries one bit; the other, its complement. The difference of the two signals measured between the two traces carries the information. A differential pair is a pair of transmission lines with some amount of coupling between the two legs of the pair.
机译:越来越多的高速标准和专有串行协议对PCB设计人员构成了主要的设计布局挑战。这些串行标准包括PCI Express,串行RapidIO,千兆以太网,XAUI / HiGig,SONET,CPRI,OBSAI以及其他许多标准。随着对高速PCB设计的需求增加,具有差分信号的串行总线正在迅速取代并行总线。差分信令使用两个输出驱动器来驱动两条独立的传输线。一个携带一位;另一个是其补充。在两条迹线之间测得的两个信号之差携带信息。差分对是一对传输线,在一对传输线的两个分支之间具有一定程度的耦合。

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