This paper explores an activity-sensitive clock gating technique for low-power design of VLSI clock networks. The concept of logic distance based on module activity information is introduced, and its relationship with the power consumption of the clock network is presented. A binary clock tree is built based on the logic distance between different modules to optimize the power consumption due to the interconnections (i.e., clock gating signals and clock edges). Also, a method for determining the gating signals with the fewest transitions is developed. After the clock tree is constructed, an additional optimization is performed on the gating signals to further reduce the power consumption.
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