A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface

摘要

In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation set-up. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space.