This paper presents very-large-scale integrated (VLSI) implementation of an infinite impulse response (IIR) temporal filtering technique for real-time stimulus artifact rejection (SAR) in bidirectional interfacing with the nervous system. The template subtraction-based, IIR-SAR algorithm is implemented on a μW-level digital signal processing (DSP) unit that initializes its embedded 16b, 4K SRAM with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. The DSP unit is integrated with spike-recording and microstimulation circuitry to create a functional, standalone, prototype system-on-chip (SoC) fabricated in AMS 0.35μm 2P/4M CMOS. The DSP unit functionality has been validated in benchtop tests using a prerecorded neural dataset from a laboratory rat, as well as in neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration of <114.7ms from the contaminated neural data in real time and recover μV-range extracellular neural spikes that occur on the tail end of the artifacts. The root-mean-square (rms) value of the pre-processed stimulus artifact is reduced on average by a factor of ~24–30 post-processing, with DSP unit power consumption of <25μW from 1.5V.
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