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基于FPGA的数字水印提取系统设计研究

         

摘要

针对信息安全问题的日益突出,提出了基于5/3整数小波的数字水印算法,给出了两种5/3小波的硬件架构:一种是基于RAM的流水线架构;另一种是基于行分组的行列并行架构。进而设计了基于FPGA的数字水印提取硬件系统,结果证明该算法具有很好的不可见性及鲁棒性,且复杂度低,硬件较容易实现,并将水印提取代码下载到FPGA硬件进行验证,结果证明该算法可以很好地实现水印的提取工作。%Since the information security problem has become increasingly prominent,a digital watermark algorithm based on 5/3 integers wavelet is proposed. Two hardware architectures of 5/3 wavelet are given:one is the pipelined architecture based on RAM,and the another is the rank parallel architecture based on row grouping. The hardware system of digital watermark ex⁃traction based on FPGA was designed. The results show this algorithm has good invisibility,robustness and low complexity,and is easy to implement with hardware. The wartermark extraction code is downloaded to FPGA for hardware verification. The verifi⁃cation results show that the system can extract the digital watermark well.

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