Domain Coverage Metric for SoC Validation

摘要

The importance of system-on-chip (SoC)validation continues to grow with the increase of designsize. An innovative domain coverage metric is proposedto measure the completeness and quality of validationapproach. Domain methodology is based on ageometrical analysis of the domain boundary and takesadvantage of the fact that the point on or near theboundary is the most sensitive to domain errors. Thecoverage tool has been implemented using Verilogprocedural interface (VPI) and applied to validation ofSoC under design. Results show that the domaincoverage can detect many design faults which statementand path coverage can not.