BIST Design for Detecting Multiple Stuck—Open Faults in CMOS Circuits Using Transition Count

摘要

This paper presents a built-in self-test (BIST) scheme for detecting all robustlytestable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. Thetest pattern generator (TPG) generates all n @ 2n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n@ 2n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counterthat counts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design- or synthesis-for-testability techniques and/or additional control lines are needed.