A fully integrated CMOS 60-GHz transceiver for IEEE802.11ad applications

摘要

A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology.The reported transceiver monolithically integrates a receiver,transmitter,PLL(Phase-Locked Loop)synthesizer,and LO(Local Oscillator)path based on a sliding-IF architecture.The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel,with an EVM(Error Vector Magnitude)of lower than−20 dB.The receiver path achieves a configurable conversion gain of 36~64 dB and a noise figure of 7.1 dB over 57~64 GHz,while consuming only 177 mW of power.The transmitter achieves a conversion gain of roughly 26 dB,with an output P1dB of 8 dBm and a saturated output power of over 10 dBm,consuming 252 mW of power from a 1.2-V supply.The LO path is composed of a 24-GHz PLL,doubler,and a divider chain,as well as an LO distribution network.In closed-loop operation mode,the PLL exhibits an integrated phase error of 3.3ºrms(from 100 kHz to 100 MHz)over prescribed frequency bands,and a total power dissipation of only 26 mW.All measured results are rigorously loyal to the simulation.