基于FPGA的1553B总线无过滤监视器设计

摘要

本文基于FPGA设计一款针对于1553B总线的无过滤监视器，其中无过滤监听包含两个层面的意思：其一，对终端的无过滤，监听总线上所有终端的数据，即针对所有类型终端的命令及回复；其二，对数据的无过滤，无论数据正确与否，监视器都将对其进行相应的处理及存储。设计采用VHDL语言实现，使用Quartus II9.0对设计实现综合、优化、仿真，最后在FPGA硬件电路上实现测试。%Based on the FPGA techn ology, a design of unfiltered monitor for the 1553B Bus is designed. The unfiltered monitor has two functions. Firstly, there is no filter at terminals. The data including the commands and replies at all the terminals of the bus are monitored. Secondly, there is no filter of data. The data are handled and stored properly in the monitor no matter whether they are wrong or false. Realized by the VHDL language, the design is synthesized, optimized and simulated based on QuartusII9.0. Finally, it is tested on the FPGA hardware circuits.