Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard

摘要

An efficient multi-rate encoder for IEEE 802.16e LDPC codes which outperforms current single rate encoders with acceptable hardware consumption and effi-cient memory consumption is proposed. This design uti-lizes the common dual-diagonal structure in parity matri-ces to avoid the inverse matrix operation which requires extensive computations. Parallel Matrix-vector multipli-cation (MVM) units, bidirectional operation and storage compression are applied to this multi-rate encoder to in-crease the encoding speed and significantly reduce the quantity of memory bits required. The proposed encoding architecture also contributes to the design of multi-rate encoders whose parity matrices are dual-diagonally struc-tured and have an Approximately lower triangular (ALT) form, such as in IEEE 802.11n and IEEE 802.22. Simu-lation results verified that the proposed encoder can effi-ciently work for all code rates specified in WIMAX stan-dard. With a maximum clock frequency of 117 MHz, the encoder achieves 3 to 10 times higher throughput than prior works. The proposed encoder is capable to switch among six rates by adjusting the input parameter and it achieves the throughput up to 1Gbps.