一种基于FPGA的PXA270外设时序转换接口设计

摘要

为解决ARCNET协议器件COM20020应用于列车通信网络时,与中央控制单元(CCU)处理器PXA270之间时序不匹配的问题.提出一种基于FPGA的PXA270外设时序转换接口设计方案.此外,还在FPGA中增加存储器直接访问(DMA)功能.以减轻PXA270的负担.测试结果表明,该方案成功解决时序匹配问题,增强网络的响应能力.关%A design of timing conversion interlace between PXA270 and peripherals based on FPGA is introduced,in order to solve the problem of timing matching when the ARCNET protocol chip COM20020 is connected to the processor of central control unit(CCU)PXA270 in train communication network. And an additional moduleDMA is designed in the FPGA to ease PXA270's burden.The test result of the whole network shows that this solution solves the timing matching problem and enhances response capability of the network.