基于H桥级联拓扑结构的中压电能质量扰动源研究

摘要

提出一种基于H桥级联拓扑结构的高压电能质量扰动源主电路拓扑方案，能够分别实现电压及电流的扰动输出。该拓扑在输出高次谐波时，采用叠波PWM调制，可以降低开关器件的等效开关频率，从而降低损耗。重点研究了该拓扑输出非整数倍谐波电流时直流电压波动的机理，针对该扰动源提出一种简单有效的直压控制策略，并通过仿真验证了相关算法。%A main circuit topological scheme of high voltage power quality disturbance source based on H-bridge cascaded topological structure is proposed. This topology can respectively realize voltage and current disturbance output. When the output is higher harmonics, the fold PWM is adopted to reduce the switching device′s equivalent switch frequency and reduce loss. The key research is the mechanism of DC voltage fluctuation when the output is non-integer times harmonic current. For this disturbance source, a simple and effective DC voltage control strategy is put forward and the related algorithm is verified through the simulation.