数字调制器载波产生电路的FPGA设计

摘要

The common approach to implement Digital Modulator Carrier producing circuit on FPGA is based on a lookup table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of digital modulator carrier on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. The system was implemented in EP1C12Q240C8, and the hardware practical test was done by embedded logic analyzer SignalTap Ⅱ of Quartus Ⅱ. The correctness and feasibility of this design is verified by practical test result.%数字调制器载波产生电路的FPGA实现通常都是基于查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源去建立庞大的查找表.文中提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源,提高运算速度.电路在FPGA芯片EPIC12Q240C8上实现,并通过QuartusⅡ嵌入式逻辑分析仪SignalTapⅡ对硬件进行了实时测试,测试结果验证了设计的正确性及可行性.