基于SVA的检验器设计方法

摘要

Assertions is the“claim for truth”and“claim for fact”in design,therefor.The sole purpose of assertions is to ensure that the designer＇s !ntent consistent with the logic circuit generation.As a new verification technology, assertion is well received by the industry insiders.0bject-oriented programming language SystmVerilog assertions（SVA）can get more support and promotion of various EDA companies.ln this paper, take the interface localbus test as an example,to illustrate how to design and use of SVA.%断言（Assertions）是关于设计所做的“真相的声明”或“事实的说明”。断言的唯一目的是保证设计者的意图与最后生成电路逻辑功能的一致性。断言作为新兴的验证技术，广泛受到业内人士青睐。面向对象编程语言SystmVerilog的断言（SVA）更是得到各家EDA公司的大力支持和推广。本文以localbus接口检验器为例，介绍如何设计和使用SVA。