Various multi-layered bus architectures are now being used in the So C industry. Reckless use of bus layers may result in low utilization of communication resource and waste silicon area. This paper introduces a quantitative analysis at the initial stage of So C design.The time complexity is examined and it is found that their scale is the order of n to the power of n, or combinatorial,and thus the problem is NP-complete. The paper proposes some heuristic methods through in-depth investigation and applies them to each step of the exploration to reduce the time complexity. The exploration processes and the proposed methods are implemented as a software program and several experiments are performed. From the results, the performance of SNP turns out to be significantly enhanced and achieves 25% enhancement in comparison with a defacto standard bus, AXI. For time complexity, the reduction ratio goes down to 3.7 × 10-6.
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