在摩尔定律面临终结的趋势下,三维集成电路技术被认为是继续提升集成电路性能和集成度的重要技术途径之一.由于采用堆叠的结构,三维集成电路适用于高密度以及异质集成应用领域.存储器是高密度集成电路的典型代表,是三维集成电路的重要应用方向之一.三维存储器技术可同时提高存储密度与访存通路带宽,是解决“存储墙”问题的一种可行技术途径.然而,由于存储器件尺寸的微缩,存储阵列中的故障存储单元数量呈增加趋势.对存储器产品,基于冗余存储资源的内建自修复技术是提高其可靠性的重要方法.三维存储器的层与层之间可通过硅通孔等技术实现互连,使得垂直方向上的冗余资源共享成为可能,从而改善三维存储器的可靠性.该文提出一种邻近层共享冗余的三维存储器修复策略,用以提高现有三维存储器内建自修复技术的故障修复能力.该策略不会引发死锁现象,具有良好的冗余资源利用率和较小的硅通孔面积代价.仿真结果表明,与已有的结对冗余策略相比,该文所提出的冗余共享策略具有更高的故障修复率,且故障修复率不随存储器层数的增加而显著下降,更适用于大规模三维存储器.%Three-dimensional (3D) integrated circuit (IC) is regarded as an important way for the enhancement on the performance and integration density of IC to cope with the challenge of "the ending of the Moore's law".The 3D IC is suitable for the high density or heterogenous integration applications for its multi-layer stacked structure.Memory is one of the important applications of 3D integration technology for it is a typical high density product.3D memory,which increases memory density and bandwidth of memory access path simultaneously,is a promising solution of the "memory wall problem".With the scaling down of memory devices,the amount of faulty cells in memory array increases rapidly,it gives rise to the requirement of the build in self-repair (BISR) technique for acceptable memory reliability.The through silicon vias (TSVs),which works as the vertical signal paths in 3D memory,enable the inter-die sharing techniques of redundant resources for higher utilization ratio.This work proposes a sharing strategy of adjacent redundant cells across dies for better repair capability.This strategy is deadlock free,and it has good utility of redundant resources and relatively small area overhead of through silicon vias (TSVs).Simulation results show that,comparing with the published die-pair sharing strategy,the proposed strategy obtains higher repair rate.Furthermore,the proposed BISR has no obvious drop of repair rate with respect to the increase of the layer count,implying a good applicability in the large scale 3D memories.
展开▼
