Novel fault-tolerant architectures forbit-parallel polynomial basis multiplier over GF(2m),which can correct the erroneous outputs using linearcode, are presented. A parity prediction circuit based onthe code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the space overhead is about 11%.Moreover, there is only marginal time overhead due toincorporation of error-correction capability thatamounts to 3.5% in case of the bit-parallel multiplier.Unlike the existing concurrent error correction (CEC)multipliers or triple modular redundancy (TMR)techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.
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