基于SOPC的交错APFC变换器设计

摘要

针对基于串行结构控制器(如MCU、DSP)设计的交错有源功率因素校正(APFC)变换器存在运行速度慢、动态特性差的问题,提出了一种基于SOPC技术控制的交错APFC变换器架构.该架构采用并行结构FPGA作为开发平台,以NiosⅡ软核处理器为核心,运行速度快,提升了系统的整体性能.文中设计了系统各模块的IP核,并构建了交错APFC变换器的SOPC系统.800 W的样机实验结果表明:该方案具有功率因素校正效果好、峰值限流能力强、动态响应速度快等优点.%Aiming at the problem of the most controllers(such as MCU and DSP) of the interleaved Active Power Factor Correction (APFC) convert have been the serial structure,which are of slow operation speed and poor dynamical characteristics,an interleaved APFC convert architecture based on SOPC is proposed in this paper.It improved the overall performance of system,because the running speed of the parallel structure FPGA platform with Nios Ⅱ soft core processor as the core.The IP core of each module of this architecture were designed and the overall SOPC system of interleaved APFC convert was constructed in this paper.Experimental results of 800 W prototype show that this method has good power factor correction effect,good peak current limiting and fast dynamic response.