Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design.The research work presented in this thesis focuses on crosstalk avoidance with bus encoding, one of the techniques that effectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption.We first derive the relationship between the inter-wire capacitive crosstalk and signal speed as well as power, and show the data pattern dependence of crosstalk. We then introduce a system that classifies busses based on data patterns. This serves as the foundation for all the crosstalk avoidance encoding techniques developed in this thesis.The first set of crosstalk avoidance codes (CACs) we present are memoryless codes. These are generated using a fixed code-book and solely dependent on the current input data, and therefore require less complicated CODECs. We develop a suite of memoryless CACs: from 3C-free to 1C-free codes. We discuss memoryless code design details and performance analysis and show that these codes are more efficient than conventional crosstalk avoidance techniques. We can speed up the bus by 100% or more with these codes with area overhead penalties from 44% to 200%. We also investigate the CODEC design for memoryless CACs and presented several solutions. The bus-partitioning based techniques divide the input bus into multiple groups and apply encoding on each group independently. Special techniques are presented to handle crosstalk across the group boundaries. These techniques allow us to achieve highly efficient designs with some area-overhead penalties. We then present two CODEC designs that are based on the Fibonacci Numeral System. The resulting designs are simple, modular, fast and requires no extra area-overhead.The second set of codes we present are memory-based CACs. Compared to memoryless codes, memory-based codes are more efficient in area-overhead. However, since the encoding/decoding processes require not only the current input data, but also the codeword from the previous cycle, the corresponding CODEC designs are more complicated. The memoryless codes we developed include a 4C-free code, which requires 33% overhead and its CODEC design is simple and fast. We also present two general memory-based codeword design techniques, namely the "code-pruning"-based algorithm and the ROBDD-based alogorithm. Experiments demonstrate that memory-based codes are more area efficient.In addition to CACs for binary busses, we also extend the crosstalk avoidance to multi-valued bus interconnects. We first generalize the crosstalk classification system to multi-level busses and then propose two ternary crosstalk avoidance schemes. Our 4X coding scheme provides 67% power saving and 2X speed up over a regular binary bus, without any area overhead. An 3X coding scheme offers an additional 33% speed improvement with 20% area overhead. We also present details about the ternary driver and receiver circuit designs.
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