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System and IC level analysis of electrostatic discharge (ESD) and electrical fast transient (EFT) immunity and associated coupling mechanisms.

机译:系统和IC级别的静电放电(ESD)和电快速瞬变(EFT)免疫力分析以及相关的耦合机制。

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摘要

The exposure of electronic circuits to lightning, electrostatic discharge (ESD), electrical fast transients (EFT) or sine wave signals can reveal RF immunity problems. Typical problems include temporary malfunctions or permanent damage of integrated circuits (ICs). In an effort to reproduce those disturbances, a series of electromagnetic compatibility standards has been developed. However, a complete understanding of the root cause of the immunity problems has yet to be established. This dissertation discusses immunity problems in three papers, starting at the system level, via the coupling path into the IC. The first paper analyzes system level ESD testing, wherein a Round Robin test was conducted at three different locations to investigate ESD test repeatability. It allowed a correlation of parameters that describe the severity of an ESD generator with respect to failure levels observed in equipments under test (EUTs). The results demonstrate the importance of the transient field generated by ESD generators for obtaining test result repeatability and indicate narrowband coupling between the ESD generator and the EUT. The second paper presents and analysis of the coupling path. This method analyzes the coupling path under the assumption of linearity in the frequency domain. Further, it shows the limitations of the small signal assumption caused by the non-linear effects of active devices. The third paper analyzes the immunity of ICs against the noise generated from EFTs with emphasis on the power delivery network (PDN). A methodology for obtaining and analyzing a circuit model of PDN inside an IC is provided. The model includes the ESD protection diodes as well as passive elements between power and ground pins. This allows estimating the current sharing of different branches within the IC and an analysis of the reaction of ESD power rail clamp to overvoltage conditions.
机译:电子电路受到雷电,静电放电(ESD),电快速瞬变(EFT)或正弦波信号的暴露会暴露出RF抗扰性问题。典型的问题包括暂时性故障或集成电路(IC)的永久损坏。为了重现这些干扰,已经开发了一系列电磁兼容性标准。但是,尚未建立对免疫问题根本原因的完全理解。本文在三篇论文中讨论了抗扰性问题,从系统层面开始,通过与集成电路的耦合路径。第一篇论文分析了系统级ESD测试,其中在三个不同的位置进行了循环测试,以研究ESD测试的可重复性。它允许参数的相关性来描述ESD发生器的严重性与被测设备(EUT)中观察到的故障水平。结果证明了ESD发生器产生的瞬变场对于获得测试结果可重复性的重要性,并表明ESD发生器与EUT之间的窄带耦合。第二篇论文介绍并分析了耦合路径。该方法在频域线性假设下分析耦合路径。此外,它显示了由有源器件的非线性效应引起的小信号假设的局限性。第三篇论文分析了IC对EFT产生的噪声的抗扰性,重点是功率传输网络(PDN)。提供一种用于获得和分析IC内部的PDN的电路模型的方法。该模型包括ESD保护二极管以及电源和接地引脚之间的无源元件。这样可以估算IC中不同分支的电流共享,并可以分析ESD电源轨钳位对过压条件的反应。

著录项

  • 作者

    Koo, Ja Yong.;

  • 作者单位

    Missouri University of Science and Technology.;

  • 授予单位 Missouri University of Science and Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2008
  • 页码 100 p.
  • 总页数 100
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

  • 入库时间 2022-08-17 11:38:36

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