Multi-carrier signaling for high-speed electrical links.

摘要

The demand for ever higher performance at lower power is motivating system designers to re-think their design strategies not just in terms of performance, but in terms of power-performance efficiency. In this new design paradigm, the performance of a communication system is mainly limited by the "total system power" constraint rather than just the "transmit power". Therefore, the choice of the optimum data communication algorithm is a strong function of circuit level power-performance trade-offs. One area where such re-thinking is vital is electrical chip-to-chip communication, where total system power-performance efficiency in terms of mWatts per Gb/s is now the key metric. Multi Gb/s chip-to-chip links find applications in the data interfaces between microprocessors, memories, peripherals, and network processing components in high performance systems.; This thesis covers the design, analysis and implementation of a multi-carrier signaling method, called Analog Multi-Tone (AMT), specifically designed to take advantage of the characteristics of chip-to-chip link systems. In our design approach power-performance efficiency is achieved through a combination of various techniques including better utilization of transmit power, parallelization of the data stream in the frequency domain, channel engineering, in-system characterization of circuits with relevant performance metrics, and eventually, careful circuit design.; We start with a study of the performance and complexity of conventional multi-tone techniques. Based on the insight obtained from this analysis, we propose a novel multi-carrier signaling technique called Analog Multi-Tone, which is customized to the link characteristics. We develop a mathematical analysis of this system including a convex framework, and closed-form jitter modeling. This analysis also provides a method of comparing the performance of this approach with alternative baseband transmission methods.; The second half of this thesis focuses on circuit design issues involved in the design of a transmitter in a 90-nm CMOS technology supporting Analog Multi-Tone as well as a variety of baseband signaling modes including 4-PAM, 16-PAM and 64-PAM, all at 24-Gb/s. We further propose a Least-Squares based characterization and digital compensation techniques for improving system performance.