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Low Dimensional Materials for Next Generation Electronics.

机译:下一代电子产品的低尺寸材料。

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摘要

Ever since the invention of the transistor, aggressive channel length scaling has been pursued to achieve higher performance and greater packing density. In order to preserve gate control at short channel lengths, the transistor channel has evolved from bulk to low dimensional substrates, such as 2D thin films and 1D nanowires. For scaling to continue, it is vital that we understand the processing and physics of low dimensional materials.;Chapter 2 focuses on quasi-2D ultrathin body InAsSb-on-insulator n-FETs. III-V materials offer high mobilities for excellent on-state currents, and by using a thin film platform we could potentially obtain good off-state characteristics. Previously we have demonstrated high performance InAs-on-insulator n-FETs. In this study we implement InAsSb transistors on SiO2 and achieve a ∼2x enhancement in effective mobility over analogous InAs devices. Top-gated devices are demonstrated with an ION/IOFF of 10 2-103 and an intrinsic conductance of ∼0.56 mS/mum.;1D InAs nanowire (NW) n-FETs are explored in chapter 3. In particular, the nanowire transistors are used to study ballistic transport, the theoretical current density upper limit. We experimentally observe ∼ 60nm channel length devices reaching ∼80% of the ballistic limit. Length dependent studies on the same nanowire are used to extract a mean free path of ∼150nm for the 1st and 2nd electron subbands. We find the mean free path to be independent of temperature, suggesting that surface roughness scattering is the dominant scattering mechanism.;Chapter 4 explores 2D transition metal dichalcogenide (TMDC) thin films. TMDC thin films offer the physical limit of scaling, and ohmic contacts to its conduction and valence bands are required for it to realize low power complementary logic. Previous studies show that elemental metal energy levels are pinned near the conduction band of TMDCs and do not offer effective hole injection. To address this we explore a high work function transition metal oxide, substoichiometric molybdenum trioxide (MoOx, x<3), as a hole injection layer to MoS2 and WSe2. MoS2 diodes and p-FETs are demonstrated with MoOx contacts. WSe 2 p-FETs with MoOx contacts show a ∼10x on-current improvement over devices with Pd contacts.;In chapter 5 we present heterojunction diodes formed by thin films of InAs and WSe2. In traditional epitaxial heterojunctions, the number of possible material combinations are limited by lattice constraints. In this study we overcome this restraint by transferring one layer upon another to form a heterojunction. Specifically, InAs/WSe2 heterojunction diodes are fabricated and measured. A forward/reverse current ratio >106, reverse bias current <10-12mum2, and ideality factor of 1.1 are observed.
机译:自从晶体管的发明以来,一直在追求积极的沟道长度缩放以实现更高的性能和更大的封装密度。为了在较短的沟道长度上保持栅极控制,晶体管沟道已从大尺寸基板演变为低尺寸基板,例如2D薄膜和1D纳米线。为使缩放继续进行,至关重要的是我们了解低尺寸材料的加工和物理原理。第二章重点介绍准2D超薄绝缘体上InAsSb n-FET。 III-V材料具有出色的导通能力,可提供出色的导通电流,通过使用薄膜平台,我们有可能获得良好的截止状态特性。以前,我们已经演示了高性能绝缘体上InAs n-FET。在这项研究中,我们在SiO2上实现InAsSb晶体管,并且在有效迁移率方面比类似InAs器件提高了约2倍。顶栅器件的ION / IOFF为10 2-103,本征电导为〜0.56 mS / mum。;在第3章中探讨了1D InAs纳米线(NW)n-FET。特别是,纳米线晶体管是用于研究弹道运输,理论电流密度上限。我们通过实验观察到〜60nm沟道长度的器件达到了弹道极限的〜80%。对同一条纳米线的长度依赖性研究被用于提取第一和第二电子子带的〜150nm的平均自由程。我们发现平均自由程与温度无关,这表明表面粗糙度散射是主要的散射机理。;第四章探讨了二维过渡金属二卤化二锡(TMDC)薄膜。 TMDC薄膜提供了缩放的物理极限,并且要实现低功率互补逻辑,就需要与其导带和价带形成欧姆接触。先前的研究表明,元素金属能级固定在TMDC的导带附近,不能提供有效的空穴注入。为了解决这个问题,我们探索了高功函数过渡金属氧化物,亚化学计量的三氧化钼(MoOx,x <3),作为MoS2和WSe2的空穴注入层。演示了具有MoOx触点的MoS2二极管和p-FET。具有MoOx触点的WSe 2 p-FET与具有Pd触点的器件相比,导通电流提高了约10倍。在第5章中,我们介绍了由InAs和WSe2薄膜形成的异质结二极管。在传统的外延异质结中,可能的材料组合数量受到晶格约束的限制。在这项研究中,我们通过将一层转移到另一层以形成异质结来克服了这种限制。具体而言,制造并测量了InAs / WSe2异质结二极管。正向/反向电流比> 106,反向偏置电流<10-12mum2,理想因子为1.1。

著录项

  • 作者

    Chuang, Steven.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 73 p.
  • 总页数 73
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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