Advanced receiver design for modernised GNSS signals

摘要

The Double Estimation Technique (DET) is a comparatively new GNSS tracking loop architecture that mitigates the ambiguity present in pseudoranges from Binary Offset Carrier (BOC) signals. These signals are part of 'modernised' GNSS development, and will see extensive use on both existing and in-development constellations. Many techniques have been proposed that either partly or wholly eliminate the problem of ambiguous BOC pseudoranges: proposal and investigation of new techniques is still an active area of research, however many of the techniques described in literature must make a trade-off between ambiguity mitigation and computational complexity. Few of the techniques have been demonstrated on hardware receivers and so knowledge of their effectiveness and practicality is limited. Comparison between the Double Estimator Technique (DET) and the commonly-used alternative Bump-Jumping (BJ) channels' operation was obtained from a hardware receiver running customised tracking channels and from simulation channels (developed from MathCAD programs supplied by Dr. Stephen Hodgart) designed to closely match the parameters of the hardware receiver. Both DET and BJ channels were compiled for the SGR-ReSI -- an FPGA-based receiver developed by SSTL as the first in the new generation of GNSS receivers. These comparison data show that an implementation of DET as described in [Blunt 2007] is not without some limitations, and this work shows how it is possible to produce in the DET a 'false-lock' condition that was previously not thought possible due to the two independent estimates. Several updates to the DET tracking architecture are herein proposed and tested, and with these additions, the DET can be made more robust to conditions that can severely disrupt operation of other techniques such as Bump-Jumping.