Design of a phase shifter with a 50ps phase resolution for a timing trigger control system for CERN's SLHC.

摘要

The SLHC (Super Large Hadron Collider) particle accelerator is the future upgrade to the current LHC (Large Hadron Collider) accelerator at CERN. The SLHC will achieve higher beam luminosity that will improve the statistical accuracy of measurements but will also increase the amount of data handled by the transmission and acquisition systems. A GBT (Gigabit Bidirectional Transceiver) ASIC is being developed which will support higher data transmission to and from the particle counting room to simultaneously handle detector data and timing, trigger, and experimental control data over the same optical link.;The thesis focuses primarily on the architecture, design and implementation of a phase shifter for the TTC (Timing Trigger and Control) system of the GBT. The TTC distributes trigger information, control information, and high precision synchronous clocks to the front end experimental electronics. The phase shifter is used by the TTC to generate multiple synchronous clocks at 40, 80, or 160 MHz that will be distributed to multiple front-end ASICs (Application Specific Integrated Circuits). The frequency and phases of these clocks can be programmed independently with a phase resolution of 50 ps to compensate for various cable/fiber lengths, time-of-flight of particles and electronic circuit delays.;The TTC phase shifter architecture is comprised of three major components: a PLL, coarse de-skew logic (CDL), and fine de-skewing logic (FDL). The PLL serves as a frequency multiplier that will phase align the clock outputs to the accelerator reference clock as well as generate the required clock frequencies needed by the CDL.;The CDL has three objectives: to generate the appropriate clock frequency to output, to set the number of internal reference clock cycles to phase shift, and to synchronize the coarse de-skewed output to the internal reference clock. The resynchronization ensures the FDL generates the proper amount of delay necessary to produce 50 ps phase resolution for the 40, 80, or 160 MHz clocks. The FDL phase generation is achieved by selecting the appropriate delay stage outputs of a DLL from an internal reference clock and the coarse de-skewed output.;An efficient architecture for the phase shifter was proposed, designed and implemented using an IBM 130nm process. Extensive simulations verify the functionality and performance of the design and show that it meets the design specifications including jitter and linearity specifications (Integral non-linearity and Differential non-linearity).