Multilevel space vector PWM for multilevel coupled inductor inverters.

摘要

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches.;A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses.;The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives.;Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains.