Process 'optimization' for surface mount printed circuit board assembly.

摘要

During the past decade, electronic products have decreased in size and weight. At the same time, their functionality has increased. Cost has always been (and continues to be) a primary concern. These market driven needs have resulted in the widespread use of fine/ultra-fine leaded pitch 'standard' surface mount devices and in the increasing popularity of leadless surface mount components, such as ball grid arrays. Along with these trends in electronics manufacturing, increased competition and a continually evolving technology are requiring manufacturing engineers to systematically improve their process to ensure 'zero defects' through extremely high first pass yields. These factors have caused the need for the development and implementation of a systematic continual process improvement strategy, which was a focus of this research.; Solder paste application concerns have become more important in electronics manufacturing as technology moves to finer lead spacing and packages. Effective and high quality surface mount techniques involve not only precise process setup but also the understanding of material characteristics and the knowledge of assembly processes. Environmental and cost concerns have resulted in the implementation of 'no-clean' processes. There are a number of differences between water-soluble and no-clean paste in terms of both processing requirements and overall chemistry. Any user moving to a no-clean process should be extremely knowledgeable about the special requirements of these pastes because such knowledge can mean the difference between an expensive high defect process and a high yield, low cost one. This is also a challenge that is faced by the most contract manufacturing environments. The orderly transition from a process that requires the cleaning step to one that does not was another focus of this research.; This research had two major objectives. The first objective was to provide and validate a systematic method to 'optimize' the surface mount printed circuit board assembly process. The process steps considered range from stencil printing through reflow soldering. The second focus was the identification of a systematic process to transition to a no-clean assembly process. Process improvement and capability studies will be performed to build up the knowledge base and to validate concepts. An in-depth understanding of process features would allow for meaningful experiments to be statistically designed and applied to model the characteristics of the stencil printing and the reflow processes. A predictable 'optimal' process can then be obtained based on these models. Guidelines for the transition to a no-clean process will be identified and validated through this research.