Recap: A novel framework for application performance optimization in recofigurable computing

摘要

Reconfigurable-computing (RC) applications employing both microprocessors and FPGAs (field-programmable gate arrays) have potential for large speedup when compared with traditional (software-based) parallel applications. However, this potential is marred by the additional complexity of these hybrid systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications' increased complexity. In this document, we explore challenges, tradeoffs, and various techniques for automated instrumentation, low-overhead measurement, hierarchical visualization, performance exploration, common bottleneck detection, and tool-assisted optimization for RC applications. We specifically propose the Reconfigurable-Computing Application Performance (ReCAP) framework to address these challenges and provide a cohesive structure for the various tradeoffs and techniques discussed. ReCAP seeks to facilitate or automate much of the time-consuming and error-prone processes associated with manually analyzing performance for an RC application, enabling an application designer to more productively locate and remedy performance bottlenecks. Through this research, novel concepts as well as infrastructure for performance analysis and optimization of RC applications are introduced, analyzed, prototyped, and evaluated. Case studies using a prototype ReCAP tool are provided across a representative set of RC systems and applications to demonstrate the effectiveness of this framework. This tool is believed to be the first of its kind for RC, a relatively new but increasingly important paradigm of computing.