Power Grid Verification

摘要

This thesis develops a collection of computer-aided design (CAD) tools for analysis and verification of the power delivery network (PDN) in integrated circuits. With technology scaling, the PDN verification problem is becoming more challenging than ever because the number of nodes that need to be checked is in the billions. There is a need for new highly efficient CAD tools that can handle the enormous sizes of today's PDNs. Existing tools are either vector-based or vectorless. Vector-based tools assume full knowledge of the currents drawn by the underlying logic circuitry and they compute the exact resulting voltage drops, while vectorless tools require a limited amount of information and they compute worst-case values for the voltage drops. Both types of tools have their own merits. The focus of the first part of this thesis is on improving the performance of an important existing vectorless technique that is based on current constraints. The second part proposes new vector-based methods for conservative verification of the PDN that will prove to be much faster than the traditional tools. Finally, the third part of the thesis introduces a new vectorless framework under transient current constraints. The new framework will be used for power scheduling, which is an emerging CAD problem for active PDNs where certain parts of the power grid can be completely shut down through power gating. A power scheduler is responsible for managing the workloads on the chip such that the PDN is kept safe from voltage drop at all time.