Amorphous ternary barriers (titanium silicon nitride) for copper/SiLK(RTM) metallization schemes: Process development and integration studies.

摘要

As the integrated circuit (IC) critical dimension (CD) shrinks, interconnect latency has emerged as a primary performance driver for IC device technologies. This has hastened the integration of copper and low-k dielectrics in back-end processing to reduce the effective signal propagation delays associated with on-chip interconnects. High-performance barrier layers capable of preventing thermal- and bias-induced diffusion of Cu ions into the low-k dielectric are essential for such metallization schemes. In this work, we present process development studies of TiSiN amorphous barrier layers and subsequent integration in Cu/SiLK™ metal/low-k dielectric stacks. The goal of this study is twofold: (1) Evaluate barrier performance for optimal TiSiN deposition parameters, and (2) Determine integration compatibility with SiLK™ low-k dielectric for comparison against SiO₂ control stacks. A modified Design of experiment (DOE) approach was used for barrier process optimization based on barrier chemical composition, microstructure and resistivity and also to evaluate process compatibility with SiLK™. Evaluation of barrier performance was undertaken to examine the thermal diffusion of Cu in various Cu/barrier/dielectric stack structures with barrier layer thickness of 25nm and 15nm. Preliminary barrier performance evaluation using Rutherford Backscattering Spectrometry (RBS), X-ray Photoelectron Spectroscopy (XPS), X-ray Diffraction (XRD) and X-ray Reflectivity (XRR) indicate stability of a 15nm TiSiN barrier layer against thermal-induced Cu ion diffusion at 450°C. Further results and discussions will be presented.