High-speed optical interconnects for video memory.

摘要

The purpose of this work has been to design, model and experimentally verify a large fast-access memory array based on the use of GaAs charge-coupled devices and an optical fiber interconnection network for synchronous clocking of the CCDs. The large memory array was to consist of 16 levels of (planar) modules with 16 large GaAs CCD memory chips (2cm x 2cm) per plane. This memory needed to be synchronously clocked so that it could deliver two dimensional pattern arrays of 4096 x 4096 pixels in 256 colors for testing high-resolution monitors.; Since the CCDs to be used had already been fabricated and tested in previous work, the present work has focused on the design and implementation of the optical interconnect scheme because experimental information is lacking here which is essential for a complete verification of the large memory array design. This effort therefore included the design of an optical receiver to be fabricated in a buffered FET Logic (BFL) process because this matches the fabrication process used for the CCDs. Thus the results of this work and the previous CCD work would serve to finalize the verification of a complete MCM (multi-chip-module) memory before construction begins. Since MCM system are costly and time-consuming to produce it is essential to demonstrate a near-to-life simulation of the system beforehand.; An integrated MSM photodetector with MESFET transimpedance amplifier with gain control capability was designed to match the GaAs CCDs fabrication process and provides necessary speed of response and gain for the photonic interconnects purpose. The issues involved in the process of optical fiber coupling to laser and photodetector were studied and modeled. Finally, the photonic interconnect link were fabricated and characterized in terms of clock skew, loss and reliability.