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Crosstalk Suppression Technique for Multi-Wire High-Speed I/O Links.

机译:多线高速I / O链路的串扰抑制技术。

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摘要

The use of differential signaling in modern high-speed serial data communication systems has enabled multiple Gb/s data rates. To sustain the growth of I/O bandwidth requirements, raising the signaling frequency of data links and the number of package I/O pins poses tremendous challenges because of the harsh signaling environment of FR4 printed circuit boards and the costs of die areas and IC packages. Simultaneous differential- and common-mode signaling can improve pin utilization and aggregate data bandwidth without increasing the signaling frequency of the high-speed transceivers. However, because inevitable transmission-line and circuit mismatches could cause signal crosstalk between the differential- and common-mode links, the achievable data bandwidth and power efficiency of this signaling approach are seriously limited.;A crosstalk cancellation technique based on the Code Division Multiple Access (CDMA) principles was proposed to suppress crosstalk in high-speed I/O systems. The technique effectively suppresses in-band crosstalk power by using a simple analog variant of CDMA. This concept has been verified by a CDMA-based four-wire signaling transceiver in a 90 nm standard CMOS technology. The transceiver achieved 16 Gb/s aggregate data rate (5.33 Gb/s/link) and 6 mW/Gb/s/wire power efficiency over four 6" FR4 PCB traces with BER 10-12. Compared to conventional simultaneous differential- and common-mode signaling systems, the CDMA-based system provides 30x ∼ 100x improvement in BER.;This thesis is focusing on the theoretical analysis and transceiver implementation of the CDMA-based crosstalk cancellation technique. Furthermore, simplified mathematic expressions of crosstalk power are derived to reasonably estimate the residual crosstalk power in both conventional and CDMA-based systems. This crosstalk analysis approach can be applied to any NRZ high-speed serial link I/O system as long as the frequency domain responses of crosstalk conversion or coupling paths can be reasonably characterized. Finally, the application of the CDMA-based technique in on-chip digital communication systems for suppressing capacitive coupling between adjacent links is discussed.
机译:在现代高速串行数据通信系统中使用差分信令已实现了多个Gb / s数据速率。为了维持I / O带宽需求的增长,由于FR4印刷电路板的恶劣信号环境以及芯片面积和IC封装的成本,提高数据链路的信号频率和封装I / O引脚的数量带来了巨大的挑战。 。同时差分和共模信令可以提高引脚利用率和聚合数据带宽,而无需增加高速收发器的信令频率。但是,由于不可避免的传输线和电路失配会导致差模链路和共模链路之间发生信号串扰,因此严重限制了该信令方法可达到的数据带宽和功率效率。基于码分多址的串扰消除技术提出了访问(CDMA)原理来抑制高速I / O系统中的串扰。该技术通过使用CDMA的简单模拟变量有效地抑制了带内串扰功率。此概念已通过90纳米标准CMOS技术的基于CDMA的四线信令收发器得到验证。该收发器通过BER <10-12的4条6“ FR4 PCB走线实现了16 Gb / s的总数据速率(5.33 Gb / s /链路)和6 mW / Gb / s /线的电源效率。 CDMA系统在BER方面提高了30倍至100倍;本文着重研究了基于CDMA的串扰消除技术的理论分析和收发器实现,并推导了串扰功率的简化数学表达式。可以合理地估计传统系统和基于CDMA的系统中的残余串扰功率,只要串扰转换或耦合路径的频域响应可以满足要求,这种串扰分析方法就可以应用于任何NRZ高速串行链路I / O系统。最后,讨论了基于CDMA的技术在片上数字通信系统中抑制相邻链路之间电容耦合的应用。

著录项

  • 作者

    Hsueh, Tzu-Chien.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 170 p.
  • 总页数 170
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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