Test vector compression techniques for systems-on-chip.

摘要

This dissertation considers the problem of test time and test data reduction for core-based systems-on-chip (SOCs). Several novel test vector compression and decompression techniques are proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a core-based design. To reduce tester memory requirements and test data bandwidth, compressed test vectors are stored on the tester and transferred to the chip where a small amount of hardware is used to decompress them. The problem of reducing test data and test application time for large SOCs can be addressed both by the core vendors and system integrators. Three different techniques that can be used by the system integrators are described. The first two techniques use run-length encoding and modified Huffman encoding to compress test vectors. The third technique uses an embedded processor to perform software decompression of test vectors. The core vendors can also use special DFT techniques targeted towards generating a smaller test data for their cores to address this problem. Three such techniques that can be used by core vendors are also described. The first of these three techniques uses a scheme combining an internal “test per clock” parallel built-in self test (BIST) methodology with conventional external testing to generate a highly compressed test set for a core. The second technique combines external scan testing with internal BIST structures to design cores with virtual scan chains, which make the core internal scan chains appear shorter in length than they actually are. Both of these techniques, however, maintain the same external test interface as a regular core with similar functionality and hence can be easily accommodated into the existing test integration methodology of system integrators. The third technique is a hybrid technique based on weighted pseudo-random BIST. This technique provides a very high test data compression compared to conventional external tester based testing but requires much less area overhead than a deterministic BIST scheme providing the same fault coverage.