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A Boolean-based layout approach and its application to FPGA routing.

机译:基于布尔的布局方法及其在FPGA布线中的应用。

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摘要

A Field-Programmable Gate Array (FPGA) is a general-purpose, multi-level programmable logic device that is customized by the end user. This thesis focuses on the final stage of a FPGA design implementation, routing. Considering the increasing complexity and capacity of current FPGA architectures, a modern FPGA router must (1) be flexible for a variety of FPGA architectures, (2) manage more accurate congestion model, and (3) be able to predict (or at least determine) the routability of the design. This thesis presents an “exact” method, called the Boolean Satisfiability (SAT)-based routing approach, that addresses all these constraints.; In Boolean SAT-based routing, a large but still atomic Boolean function is created such that its internal structure represents the geometric routing constraints. Any satisfying assignment of Boolean values to variables in this function corresponds to a legal routing solution. Compared to traditional routers which sequentially consider one net at a time, this approach offers two unique features: (1) simultaneous embedding of all nets regardless of net ordering and (2) the ability to demonstrate routing infeasibility by proving the unsatisfiability of the routing constraint Boolean function.; This Boolean-based routing approach was implemented and applied to both final detailed routing and fault tolerant FPGA reconfiguration, which is a partial routing task. Also, to make this method more practical, a hybrid routing algorithm, which combines a conventional routing approach with our SAT-based routing flow, was devised and tested with industrial-sized circuits. Experimental results show that Boolean SAT-based routing is a viable complement to existing routing approaches. In particular, when integrated within the flow of conventional routers, SAT-based routing solves their non-convergence problem by its ability to prove unroutability of the current set of route alternatives. For reconfiguration applications, SAT-based routing is very competitive, in flexibility, quality and runtime, with conventional approaches. These promising results suggest that SAT-based methods may have a useful role to play in other layout applications.
机译:现场可编程门阵列(FPGA)是由最终用户定制的通用,多层可编程逻辑设备。本文着重于FPGA设计实现的最后阶段,即路由。考虑到当前FPGA架构的复杂性和容量日益增加,现代FPGA路由器必须(1)灵活适用于各种FPGA架构,(2)管理更准确的拥塞模型,以及(3)能够预测(或至少确定)设计的可路由性。本文提出了一种“精确的”方法,称为基于布尔可满足性(SAT)的路由方法,该方法解决了所有这些约束。在基于布尔SAT的路由中,将创建一个大型但仍为原子的布尔函数,以使其内部结构表示几何路由约束。在此函数中,对变量的布尔值的任何令人满意的分配都对应于合法的路由解决方案。与传统的路由器一次一次考虑一个网络相比,这种方法具有两个独特的功能:(1)同时嵌入所有网络,而不管网络顺序如何;(2)通过证明路由约束的不满足性来证明路由不可行布尔函数。这种基于布尔的路由方法已实现,并应用于最终的详细路由和容错FPGA重新配置,这是部分路由任务。此外,为使此方法更实用,还设计了一种混合路由算法,并将传统的路由方法与我们基于SAT的路由流程相结合,并通过工业规模的电路进行了测试。实验结果表明,基于布尔SAT的路由是对现有路由方法的可行补充。特别是,当集成在常规路由器的流程中时,基于SAT的路由可以证明其当前路由选择集的坚固性,从而解决了它们的不收敛问题。对于重新配置应用程序,与传统方法相比,基于SAT的路由在灵活性,质量和运行时间方面都非常有竞争力。这些有希望的结果表明,基于SAT的方法可能在其他布局应用程序中发挥有用的作用。

著录项

  • 作者

    Nam, Gi-Joon.;

  • 作者单位

    University of Michigan.;

  • 授予单位 University of Michigan.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 110 p.
  • 总页数 110
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

  • 入库时间 2022-08-17 11:46:52

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