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Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance.

机译:用于利用寄存器改善内存性能的编译器和微体系结构机制。

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摘要

The performance of the memory hierarchy has become one of the most critical elements in the performance of desktop, workstation and server computer systems. This is in large part due to the growing gap between memory and processor speed and the large number of memory operations present in typical programs. This problem is called the memory bottleneck. There are a number of techniques for containing this problem, including register allocation, caching, and prefetching. These techniques, which either eliminate memory operations or reduce their apparent effect, can be implemented in either hardware or software. This dissertation presents combined hardware and software methods to implement and manage the register file more effectively, with the primary focus to eliminate memory operations.; This dissertation first examines the register requirements of integer codes and shows that a combination of advanced compiler optimizations combined with a large register file can improve performance up to 45%. The improvements show the importance of a large register file to integer codes. Although a large number of registers is good from the compiler's perspective, a large register file can be slow and expensive to build. This dissertation proposes a new caching technique that retains the advantages of a large register file without the speed and cost penalties.; Studies of existing compiler optimizations showed that a common optimization called register promotion, which increases the utilization of the register file and reduces memory operations, is limited by static alias analysis in the compiler. This dissertation introduces a new compiler optimization called speculative register promotion and a new hardware structure called the store load address table to address this problem.; This dissertation also proposes several new metrics to measure compiler performance in units of hardware complexity and examines memory accesses in the context of their programming language source code in order to determine the relative importance and characteristics of these memory operations.; The dissertation concludes with an examination of a new research compiler for the C programming language called MIRV that was used to perform this research. Various aspects of the compiler and engineering trade-offs made during its design are explained.
机译:内存层次结构的性能已成为台式机,工作站和服务器计算机系统性能中最关键的元素之一。这在很大程度上是由于内存和处理器速度之间的差距越来越大以及典型程序中存在大量内存操作所致。这个问题称为存储瓶颈。有许多技术可以解决此问题,包括寄存器分配,缓存和预取。这些消除内存操作或降低其明显效果的技术可以用硬件或软件来实现。本文提出了软硬件相结合的方法,以更有效地实现和管理寄存器文件,其主要重点是消除存储器操作。本文首先研究了整数代码的寄存器要求,并表明将先进的编译器优化与大型寄存器文件相结合可以将性能提高多达45%。改进表明大型寄存器文件对于整数代码的重要性。尽管从编译器的角度来看,大量的寄存器是好的,但是大型的寄存器文件构建起来可能很慢且昂贵。本文提出了一种新的缓存技术,该技术保留了较大的寄存器文件的优点,而没有速度和成本的损失。对现有编译器优化的研究表明,称为寄存器提升的常见优化受编译器中的静态别名分析限制,该优化可提高寄存器文件的利用率并减少内存操作。本文介绍了一种新的编译器优化方法,称为推测寄存器提升,以及一种新的硬件结构,称为存储加载地址表,以解决此问题。本文还提出了几种新的度量标准,以硬件复杂度为单位来衡量编译器的性能,并在其编程语言源代码的上下文中检查存储器访问,以确定这些存储器操作的相对重要性和特征。论文的结尾是对用于执行此研究的名为MIRV的C编程语言的新研究编译器的研究。解释了编译器的各个方面以及在其设计过程中进行的工程折衷。

著录项

  • 作者

    Postiff, Matthew Allan.;

  • 作者单位

    University of Michigan.;

  • 授予单位 University of Michigan.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 224 p.
  • 总页数 224
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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