Portable devices, such as mobile phones, personal digital assistants, notebooks, etc., have become an indispensable part of our daily life. Mobility requires energy autonomy, which is achieved with the use of batteries. Due to stringent size and weight requirements, batteries do not last sufficiently long under high-power loads, counteracting many of the perceived benefits of mobile computing and communications. Consequently, energy efficiency has become one of the key design challenges.; This dissertation studies two different approaches toward the design a set of interdependent tasks, executed by the system, as a time-varying load on the battery. We assume that the system can operate at multiple supply voltages and clock frequencies. The goal is to develop algorithms for energy-aware task scheduling, exploiting the capability of changing the supply voltage and the clock frequency. Automated optimization of energy efficiency for battery-powered systems is inadequate without accurate predictions of the available energy, i.e. the lifetime of the battery, under a given load. Therefore, a key component of this effort involves the development of a robust model of battery behavior and efficient methods for predicting battery lifetime.; The second part of this dissertation explores hardware-software cosynthesis for reconfigurable processors, with energy efficiency as the main objective. Hardware components in such processors can be reconfigured to respond to changes in user demands. Reconfigurability allows for system flexibility, thus reducing product volatility, time-to-market and cost of development and manufacturing. Even though hardware programmability offers a variety of benefits, the reconfiguration cost in terms of power dissipation and delay is the key factor limiting system performance. To address energy and delay issues associated with reconfiguration, we develop a method for binding user program blocks either to a software execution unit or to a reconfigurable hardware execution unit, accounting explicitly for energy and delay penalties due to both computations and configurations. In addition, we describe the organization of the reconfigurable hardware space that allows for simple dynamic placement and routing of hardware objects, and propose an efficient method for reducing the amount of reconfiguration during routing in such environment.
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