Recent studies suggest that synthesis and optimization under the physical hierarchy is a promising way to achieve timing closure between synthesis and layout for deep submicron designs. In this PhD dissertation, we focus on how to build a good physical hierarchy for performance optimization. The logical hierarchy is first flattened to the extent that we are certain circuit elements in each module have "physical locality" i.e., the circuits in a module should physically stay together, and then coarse/global placement is performed on this flattened design to place the placeable objects and generate a physical hierarchy. We adopt the multi-level optimization paradigm for it.;First, a multi-level coarse placement framework for physical hierarchy generation, MPG, is developed for wirelength minimization. The placement engine is based on the simulated-annealing technique because of its flexibility of integrating various design objectives and handling constraints. Experiments show that, compared to GORDIAN-L, the wirelength-driven MPG is 3--6 times faster and generates slightly better wirelength for test circuits larger than 100K cells. Compared with wirelength-driven DRAGON, it provides a slightly longer wirelength (2--5%) with 25--50% runtime reduction for large designs.;Second, in order to handle large-scale IC designs with standard cells mixed with blocks, based on MPG, a placement algorithm, MPG-MS, is proposed to simultaneously place objects with large size variations. The big placeable objects are gradually fixed and any overlap between them is gradually removed, while small object placement is further refined during the multi-level optimization process. Experiments on large-scale mixed-size placement benchmarks show that MPG- MS can outperform a recent published work [1] by 13% on average in terms of total wirelength.;Third, in order to handle performance optimization, particularly to use the retiming technique to optimize the long interconnect, a practical solution for integrating retiming into the multi-level global placement for large-scale designs, MPG-RT, is proposed. It is based on the theory and algorithms of sequential timing analysis. Experiments show that (i) retiming can improve the performance (delay) by 14% on average when it is applied after placement; (ii) our approach for simultaneous retiming and placement can outperform the two-step approach (placement followed by retiming) by 10% on average in terms of delay minimization.
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