There are many standards for high-speed interfaces which logically describe the behavior specification, but not how to achieve the behavior as a function of performance and design tradeoffs. There is very little published standard methods for modelling and simulating an end-to-end high-speed links. This research dissertaion describes methods for modeling and designing high-speed equalizers. The development of a system modeling framework to explore the design space of SerDes high speed links uses the combination of measured channel behavior parameters inserted into an appropriate mix of simulation tools. The s-parameter characterization of channels combined with models of equalization architectures are used to explore the system design. A multi-level modeling technique is described which combines the high level design abstraction in Matlab with the benefits of measured low level models such as transistor level SPICE.;The modeling techniques described in this paper are used to develop the following design considerations: (1) combination of taps in Viterbi-DFE to reduce the overall complexity of the equalization scheme (2) how to determine the bit error rate at 10-15 and lower; and (3) effect of crosstalk and jitter on the hybrid behavior.
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