Complexity-effective instruction queues for high-performance processors.

摘要

Processor performance is highly related to the clock cycle time and Instructions per Cycle (IPC) count. Increase in clock speed has been made possible by improvements in silicon technology and careful processor design. On the other hand, increases in IPC have mainly resulted from using more complex hardware logic on the chip. With the very complex nature of current microprocessors, it is becoming increasingly difficult to further speedup the clock rates. Instruction Queue (IQ) logic lies at the heart of current superscalar processors, and is responsible for issuing multiple instructions in parallel. It is one of the most complex and power hungry modules in out-of-order processors. Having large IQs and issue widths to increase IPC has a negative effect on clock speed. On the other hand, increasing the clock speed by means of deeper pipelining hurts the IPC.; In this dissertation, I discuss complexity-effective IQ designs for high performance. IQ complexity is directly related to the IQ size and the processor issue width. Complexity reduction can therefore be achieved (without directly reducing these parameters) by reducing either (i) the effective queue size considered for issue or (ii) the effective number of results used for identifying data-ready instructions. In this regards, I discuss different techniques for reducing the IQ logic complexity. The first technique, that has already been proposed, partitions the IQ into smaller independent IQs (thus reducing the number of instructions considered for issue in each smaller IQ). Unfortunately, such multi-PE reduced IQ complexity processors suffer from a significant limitation that the IPCs obtained with them is low. Hence, I propose a novel technique of instruction replication to remedy this limitation, thus obtaining complexity-effective partitioned IQ designs (i.e. reduced complexity with negligible IPC loss). Other techniques that I propose for reducing IQ complexity use program characteristics to reduce the effective queue size considered for issue and the effective number of results used for identifying data-ready instructions. The new set of complexity-effective IQ designs, that use program characteristics to reduce IQ complexity, significantly reduce the IQ logic delay and power consumption while maintaining the IPC.; In the future, with increased number of transistors integrated on the chip, processors can be designed with larger IQs and issue widths. It is imperative that the complexity-effective IQ designs remain effective at larger IQ sizes and issue widths. Hence, I study the scalability of both the partitioned IQs (in multi-PE processors) and the new IQs proposed in the dissertation. My results indicate that conventional partitioned IQs are not scalable. However, partitioned IQs with instruction replication as well as the new IQs (exploiting program behavior) are very scalable.