Transaction level model based performance estimation and system generation.

摘要

Embedded system design faces severe challenges in terms of high design complexity and tight time-to-market pressure. To address the challenges, aggressive reuse of existing components and highly flexible design is becoming a must throughout a system design process. To obtain strong re-usability and high flexibility, recent design paradigm is rapidly shifting to platform based design using software intensively, in which heterogeneous multiprocessor platforms are increasingly being used to deal with growing complexity and performance demands of modern applications. In such a platform based design, a design methodology should address three important procedures: (a) choosing the optimal platform for a given application, (b) finding the optimal mapping of the application to the platform, and (c) automatic system generation from system level design decisions.;The accurate analysis of system performance for a given design decision can guide (a) and (b). It requires early and accurate estimation of performance including insight into effects of dynamic scheduling and RTOS overhead. Traditional approaches make use of instruction set simulation models (ISS) for cycle accurate performance analysis on software. However, binary interpreting ISS is too slow to explore design space efficiently. Due to its speed limitation, an ISS-based model cannot be acceptable when coping with complex platforms with a lot of software. In addition, ISS is lack of a RTOS support that is essential to analyze performance of the system because RTOS puts a significant impact on the overall system performance. For practical performance analysis, fast and accurate estimation of software performance with abstract RTOS modeling is a promising solution for rapid design space exploration and early prototyping. Along with rapid design space exploration at early design stage, (c) is required to provide best productivity gain in the design process. To realize (d), a proper tool support with well defined design steps is required.;In this thesis, we presents a novel performance estimation technique for automatically generated cycle-approximate transaction level models (TLMs) integrated with timed RTOS modeling. To enable automatic system generation out of system level design decisions, system generation engine is introduced at the end of the thesis. For the performance estimation, the inputs are application C processes, their mapping to processing units in the platform, and RTOS configuration. The processing unit model consists of (pipelined) datapath, memory hierarchy and branch delay model. Using the processing unit model, the basic blocks in the C processes are analyzed and annotated with estimated delays. This is followed by a code generation phase where delay-annotated C code is generated and linked with time RTOS model. The timed RTOS model emulates RTOS behavior and takes the overhead of RTOS primitive operations into account, such as context switch, scheduling, and interrupt handling. System generation engine inputs platform specification with system level decisions and outputs the final implementation model that is runnable on the FPGA board.;We demonstrate the applicability of our techniques using multi-core platform executing a JPEG encoder and/or MP3 decoder those are industrial scale designs. Experiments show that timed TLMs, along with timed RTOS model, can be automatically generated under 1 minute. Each TLM simulates under 1 second, compared to more than 5 hours of instruction set simulation (ISS) and 20 hours of RTL level simulation. Comparison to on-board measurement showed only 8% error on average in estimated cycles. The system generation engine also outputs a final implementation out of system level design decisions under 1 second. Comparing to the manual generation, the engine can provide more than 1000 X productivity gain, while letting designers focus on system level design decisions by realizing automatic system generation.