Comprehensive Multi-level Joint Optimization for Multi-mode FIR-like Structures.

摘要

FIR filters are vastly used in multi-mode systems where the behavior of the system changes based on user inputs or changes in the operational environment. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). Partially reconfigurable FPGA platforms are shown to be viable choices to implement multi-mode filters. For multi-mode FIR filters, the area, power and performance of the filters implemented for each mode of operation can be optimized based on the value of the coefficients. However this makes the structure dependent to the coefficient set used to optimize it. In other words optimizing the area of the filters leads to increasing the reconfiguration delay. In this thesis, I propose to split the filter structure into two sections: a static section and a reconfigurable section. While the static section stays the same across all modes of operations, the reconfigurable section is optimized for each mode. I propose a polynomial time solution to minimize the size of the reconfigurable section for the given value of coefficients. Minimizing the reconfigurable section of a filter minimizes the area to be reconfigured. However since the filter structures in a given sequence of designs, share common subsets of coefficients, we can reduce the reconfiguration overhead by NOT reconfiguring the common substructure between the subsequent designs. To exploit the similarity, we suggest an approach to jointly optimize a given sequence of filter structures. The objective is to reduce a linear cost function of area and reconfiguration overhead. Joint optimization approach is effective to exploit similarity across filters. However the area and reconfiguration overhead can only be determined after physical implementation of a circuit. In this thesis, I propose to augment our joint optimization approach with an optimization approach at physical level. The objective of the optimizations is to minimize the area of the design while fully exploiting reusable modules across designs. In this thesis I theoretically study the abovementioned problems and propose efficient solutions to solve them. As the result of this work, I have developed a tool which gets the description of a sequence of filters as an input and generates the RTL design of the filters in VHDL code. It then gives hints on how to place the modules of the design to physical regions on the FPGA chip. The results show the importance of this approach and the efficiency of the solutions proposed.