Quadrature Down-converter for Wireless Communications.

摘要

Future generation of wireless systems will feature high data rates and be implemented in low voltage CMOS technologies. Direct conversion receivers (DCRs) will be used in such systems which will require low voltage RF front-ends with adequate linearity. The down-converter in a DCR is a critical block in determining linearity. In addition to detailed DCR modeling in MATLAB, this thesis, completed in 2005, deals with the design and characterization of a 1V, 8GHz quadrature down-converter. It consists of two mixers and a quadrature generator implemented in a 0.18µm CMOS technology.;The mixer architecture proposed in this work uses a new trans-conductor. It simultaneously satisfies the low voltage and high linearity requirements. It also relaxes the inherent trade-off between gain and linearity governing CMOS active mixers. The implemented mixer occupies an area of 320 x 400 µm 2 and exhibits a power conversion gain of +6.5dB, a P-1dB of -5.5dBm, an IIP3 of +3.5dBm, an IIP2 of better than +48dBm, a noise figure of 11.5dB, an LO to RF isolation of 60dB at 8GHz and consumes 6.9mW of power from a 1V supply.;The proposed quadrature generator circuit features a new architecture which embeds the quadrature generation scheme into the LO-buffer using active inductors. The circuit offers easy tune-ability for process, supply and temperature variations by relaxing the coupling between amplitude and phase tuning of the outputs. The implemented circuit occupies an area of 150 x 90µm 2 and exhibits an amplitude and quadrature phase accuracy of 1 dB and 1.5° respectively over a bandwidth of 100 MHz with a power consumption of 12mW from a 1V supply including the LO-buffer.;The quadrature down-converter features an image rejection ratio of better than 40 dB and satisfies the potential target specifications of future mobile phones, extracted in this work.