Future transistor scaling will require enhancement in device electrostatics (multigate), channel transport enhancement (beyond strained Silicon) and reduction in parasitics (contact, junction engineering etc.). Due to the high electron mobility and hole mobility (using strain), antimony (Sb) based III-V materials are of strong interest as channel material for low power all-antimonide complementary metal-oxide-semiconductor (CMOS) digital logic. Sb-based MOSFETs can operate at high speed and very low supply voltage, which promises to dramatically lower the power dissipation in future high-speed logic circuits.;This dissertation will describe compound semiconductor based transistor architecture which integrates mixed anion InAsxSb1-x quantum-wells (QW) exhibiting very high electron mobility, for ultra-low power logic applications. I will discuss the following aspects of the n-channel Sb MOSFETs using experimental data and detailed modeling: a) material selection and device design; b) strategy for integrating a high-k dielectric using a composite barrier scheme; c) equivalent oxide thickness scalability including quantum capacitance; and d) transport properties in long and short channel Sb NMOSFETs. The dissertation concludes with benchmarking the performance of Sb NMOSFETs with other III-V devices, and address the feasibility of Sb NMOSFETs for enhancement mode (normally OFF) logic transistors operating with ultra low energy dissipation.
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