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Performance evaluation and low power design of network processors.

机译:网络处理器的性能评估和低功耗设计。

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摘要

As network line rate increases exponentially and new network applications and protocols are deployed, it is a challenge to accomplish both high-speed and versatile packet processing tasks in the future Internet. Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers and switches. Typical NPs have optimized instruction set for packet processing and incorporate multiprocessing and multi-threading to achieve maximum parallel processing capabilities. This dissertation first studies the typical workload of an IP router and evaluates the performance of proposed shared memory multiprocessor routers for high-speed networks. To enable both performance and power consumption research of NPs, NePSim is then built as the first open source NP simulator with cycle-level accuracy and power evaluation framework. This dissertation presents the validation of NePSim and performance and power simulation results of four representative benchmark applications using NePSim. Processing Elements (PEs) are the key components responsible for processing packets in an NP. As more PEs are added onto an NP and the clock frequency of the chip increases, the power consumption of NPs has become a major concern. Two power saving techniques for NPs---Dynamic Voltage Scaling (DVS) and clock gating---are proposed. DVS exploits the idle time of PEs and dynamically adjusts the voltage and operational frequency of NPs. The experiment data shows that the power saving using DVS can reach up to 17% with only 6% reduction of the system throughput. The low power design of NP using clock gating is motivated by the observation that under low incoming traffic rates, most PEs in NPs are nearly idle and yet still consume dynamic power. Clock gating reduces the activities of PEs according to the varying traffic volume. Simulation results show that the technique brings significant reduction in power consumption (up to 30%) with no packet loss and little impact on the overall throughput.
机译:随着网络线路速率呈指数级增长,并且部署了新的网络应用程序和协议,在未来的Internet中完成高速和通用数据包处理任务是一项挑战。网络处理器(NP)已成为成功的平台,可在构建强大的路由器和交换机时提供高性能和灵活性。典型的NP具有针对数据包处理的优化指令集,并结合了多处理和多线程以实现最大的并行处理能力。本文首先研究了IP路由器的典型工作量,并评估了所提出的用于高速网络的共享存储器多处理器路由器的性能。为了同时进行NP的性能和功耗研究,然后将NePSim构建为第一个具有周期级准确性和功耗评估框架的开源NP仿真器。本文介绍了NePSim的验证以及使用NePSim的四个代表性基准测试应用的性能和功率仿真结果。处理元素(PE)是负责处理NP中数据包的关键组件。随着更多的PE被添加到NP上并且芯片的时钟频率增加,NP的功耗已成为主要问题。提出了两种用于NP的节能技术-动态电压缩放(DVS)和时钟门控-。 DVS利用PE的空闲时间,并动态调整NP的电压和工作频率。实验数据表明,使用DVS可以节省多达17%的功率,而系统吞吐量仅降低6%。使用时钟门控的NP进行低功耗设计的原因是,在低传入流量速率下,NP中的大多数PE几乎都处于空闲状态,但仍消耗动态功率。时钟门控根据流量的变化减少了PE的活动。仿真结果表明,该技术可显着降低功耗(最多30%),而不会丢失数据包,并且对总体吞吐量的影响很小。

著录项

  • 作者

    Luo, Yan.;

  • 作者单位

    University of California, Riverside.;

  • 授予单位 University of California, Riverside.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2005
  • 页码 124 p.
  • 总页数 124
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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