System-level Power Prediction Methodology for Mobile 3-D Graphic Engines.

摘要

In this dissertation, we introduce an electronic system-level (ESL) methodology that predicts power consumption of 3-D integrated circuits (ICs) with through-silicon vias (TSVs). This methodology is implemented using SystemC transaction-level model (TLM). For the targeting application that shows a high potential in TSV integration, we choose mobile graphic engines that are widely used in smartphones and tablet computers. For both 2-D and 3-D GPU architectures, this methodology is executed in two stages. In the first stage, we achieve an accurate power prediction by incorporating register transfer level (RTL) physical design flow into the TLM core program. In the second stage, we execute the TLM core where power consumption is computed for each instruction organized into multiple command blocks that represent logic, memory and interconnects. In addition, we introduce oorplanning of the command blocks to make an accurate prediction of interconnect power. Using this methodology, we present a case study on an open-source GPU. Based on this case study, our TLM model achieves an average of 92.2 percent accuracy in power consumption values compared to its RTL counterpart, while reducing the total CPU time of synthesis and routing to a factor of 2.52 and power computa- tion to a factor of 14. Furthermore, the reconfiguration cost of the TLM model in terms of the number of lines in SystemC codes is reduced by an average of 21 percent using thread-focused programming. For the power consumption values, an average of 27.4 percent savings in power consumption with the integration of TSV wide I/Os are reported.