An algorithmic wide -range synchronization system based on a predictive phase locked loop architecture.

摘要

An algorithmic wide-range synchronization system for applications in utility and non-utility power systems and power electronics is presented. The synchronization system is based on a predictive phase locked loop (PPLL) architecture. The PPLL is fully adaptive in extracting time variant synchronization information from an input signal. The fundamental component of the input signal is extracted in the form of three equidistant samples using a fundamental sample extractor. The synchronization information includes frequency, amplitude, and phase angle with respect to a reference frame that can be altered so as to allow a real-time phase offset implementation. A set of requirements for utility and non-utility applications is developed. The PPLL can extract the synchronization information from the input signal over a wide range of frequency and amplitude in the presence of disturbances. Two methods are developed to extract the synchronization information. The strengths of each method are exploited so as to achieve high execution speed and low real estate utilization. The mathematical properties of the two methods are presented. The synchronization system is implemented on a field programmable gate array (FPGA). The operating range for frequency and amplitude are from a fraction of Hz to a few kHz and from 4% to 100% of nominal amplitude respectively. The synchronization information is extracted within two cycles of the input signal period under any realistic perturbations in frequency, amplitude, and/or phase angle. The proposed synchronization method is faster, more flexible and more robust than the currently available methods.