Adaptive Receivers for High-Speed Wireline Links.

摘要

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver.;First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye.;In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.