A high speed and multichannel Data Acquisition System for the ARIANNA High Energy Neutrino Detector.

摘要

The ARIANNA (Anarctic Ross Ice-shelf ANtenna Neutrino Array) experiment is designed to detect high energy neutrinos in excess of 10 17eV. It will consist of over nine hundred stations deployed on the Ross Ice Shelf in Antarctica. Each station includes radio frequency antennas, amplifiers and a data acquisition (DAQ) system. Each DAQ system contains four channel analog transient waveform digitizer (ATWD) circuits, two stages of the FPGA auxiliary circuitry, a 32 bit micro controller and both satellite and local-area wireless networking. Each station is powered by sun and wind.;The ATWD circuitry, which is essentially an oscilloscope on a chip, operates with a 2 GHz sampling rate and achieves over 11 bits of dynamic range. The circuits sample continuously over a 128-deep switched capacitor sample and hold analog storage array arranged in a circular fashion. Unlike previous designs, the high-speed sample clocking is synchronous and has very high timing stability due to the use of a phase-locked loop, resulting in about 1 part per million RMS jitter.;The core DAQ system comprises four channels of ATWD sampling with extensive supporting electronics. The four ATWD's acquire signals simultaneously and can produce a real-time trigger based on pattern matching of the incoming waveforms. A programmable logic array (PLA) in each chip searches for patterns in the incoming samples to find signals of interest, for example a bipolar impulsive waveform within a certain magnitude and frequency range. Each pattern can be any combination of 8 high (H), low (L), intermediate (I) or don't-care (X) conditions, using two thresholds, one high and one low. Thus, for example, a pattern such as "HILXXXXX" requires the first sample be above the high threshold, the next sample to be between the high and low threshold, the third sample to be below the low threshold, and any condition for the remaining samples. Up to 72 patterns can be searched for in parallel, leading to a great deal of flexibility in the sort of signals that can be searched for. Once an ATWD's trigger indicates that a match has been found, logic in the system's FPGA's can then look for timing coincidences that indicate multiple ATWD's have seen the same radio signal. If a programmed level of coincidence (e.g., three out of four ATWD's) occurs over a preset period of time, a master trigger is delivered and the ATWD's are halted. An on-board 32-bit embedded computer system then supervises the digitization of the ATWD's contents, and saves it in flash memory and/or transmits the resulting data to U.C. Irvine for further processing.;This multi-level trigger system has the advantage over what a simple threshold could accomplish. The combination of the high and low thresholds, PLA patterns, and the use of coincidence logic in the system results in a multi-level, real-time smart triggering system, which is designed to positively identify genuine signals, and drastically decrease the number of the false triggers due to noise by perhaps three or more orders of magnitude.